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? semiconductor MSM7653 1 ? semiconductor MSM7653 ntsc/pal digital video encoder general description the MSM7653 is a digital ntsc/pal encoder. by inputting digital image data conforming to itu rec. 656 or iturbt 601, it outputs selected analog composite video signals, analog s video signals. for the scanning system, interlaced or noninterlaced mode can be selected. since the MSM7653 is provided with pins dedicated to overlay function, text and graphics can be superimposed on a video signal. in addition, this encoder has an internal 10-bit dac. so, when compared with using a conventional analog encoder, the number of components, the board space, and points of adjustment can greatly be reduced, thereby realizing a low cost and high-accuracy system. the MSM7653 provides the optional functions such as macrovision rev. 7.01 (note 1) (note 2) and closed caption signal generation function. the host interface provided conforms to philips's i 2 c specifications, which reduces interconnections between this encoder and mounting components. the internal synchronization signal generator (ssg) allows the MSM7653 to operate in master mode. features ? video signal system: ntsc/pal ? scanning system: interlaced/noninterlaced (ntsc : 262 lines/pal : 312 lines) ? input digital level: conforms to itu-r601 (ccir601) ? input-output timing: conforms to itu rec. 656 or iturbt 624-4 ? input signal sampling ratio : y:cb:cr = 4:2:2 ? supported input formats itu rec. 656 ycbcr 27 mhz format (8-bit input) itu-r601 13.5 mhz (8-bit (y) + 8-bit (cbcr) input) ? sampling frequency : 27 mhz ? internal ssg circuit (can operate as a master in other operation modes than ccir rec. 656 mode) ? internal 3ch 10-bit dac ? 3-bit title graphics can be displayed ? color bar function ?i 2 c-bus host interface function ? 3.3 v single power supply (each i/o pin is 5 v tolerable) ? closed caption function ? macrovision rev. 7.01 ? package 56-pin plastic qfp (qfp56-p-910-0.65-2k) (product name: MSM7653gs-2k) preliminary this version: jun. 1998
MSM7653 ? semiconductor 2 applications ? set top box ? dvd ? digital vtr (note 1) this device is protected by u.s. patent numbers 4631603, 4577216 and 4819098 and other intellectual property rights. the use of macrovision corporation's copy protection technology in the device must be authorized by macrovision and is intended for home and other limited pay-per-view uses only, unless otherwise authorized in writing by macrovision. reverse engineering or disassembly is prohibited. (note 2) refer to the macrovision anticopy function setting machine for the copy protection.
? semiconductor MSM7653 3 block diagram sync generator & timing controller prologue block i 2 c control logic test control logic ipf overlay control yuv color generator reset_l black & blank pedestal interpolator + lpf interpolator + lpf color burst generator y level converter u level converter v level converter anticopy function block closed caption block olc olg olb cd[7:0] clkx2 mode clkx1o clksel scl sda adrs subcarrier generator tenb test1 cvbso ms sel[2:1] blank_l hsync_l vsync_l yd[7:0] olr dac ipf ya dac ipf ipf = interpolation filter ca dac vref fs outsel comp
MSM7653 ? semiconductor 4 pin configuration (top view) nc : no-connection pin 56-pin plastic qfp 1 56 55 54 53 52 51 50 49 48 47 46 45 44 43 15 16 17 18 19 20 21 22 23 24 25 26 27 28 dgnd test1 tenb vref fs comp agnd ca av dd cvbso agnd ya av dd dgnd dgnd yd0 yd1 yd2 yd3 yd4 yd5 nc yd6 yd7 blank_l hsync_l vsync_l dgnd 2 3 4 5 6 7 8 9 10 11 12 13 14 42 41 40 39 38 37 36 35 34 33 32 31 30 29 dv dd ms sda scl adrs reset_l mode olc olr olg olb clkx1o outsel dv dd dv dd sel2 sel1 clksel cd0 cd1 cd2 cd3 cd4 cd5 cd6 cd7 clkx2 dv dd
? semiconductor MSM7653 5 pin descriptions (1/2) pin i/o symbol description 1dv dd 3.3 v digital power supply 2ims selects between master and slave at 27 mhz or 13.5 mhz ycbcr operation. pulled down 3 i/o sda i 2 c interface data bus 4 i scl i 2 c interface clock bus 5 i adrs i 2 c-bus slave address setting pin ("0" : 1001100 / "1" : 1001110). pulled down 6 i reset_l system reset signal. negative porality 7 i mode broadcasting mode select pin. "0" : ntsc/"1" : pal. pulled down 8 i olc transparent control signal. "1" indicates overlay signal. normally fixed to "0". 9 i olr overlay text color (red component). normally fixed to "0". 10 i olg overlay text color (green component). normally fixed to "0". 11 i olb overlay text color (blue component). normally fixed to "0". 12 o clkx1o 13.5 mhz divided clock output signal 13 i outsel normally fixed to "0". pulled down 14 dv dd 3.3 v digital power supply 15 dgnd digital gnd 16 i/o vsync_l vertical sync signal input/output pin (itu656: o, ycbcr: i/o) negative polarity 17 i/o hsync_l horizontal signal input/output pin (itu656 : o, ycbcr: i/o) negative polarity 18 i blank_l composite blank signal. negative polarity. see the description on page 15 for the operating requirement. 19, 20 i yd7 to yd6 msb 2 bits of 8-bit digital image data input pins (for itu656 and ycbcr 27 mhz). level conforms to itu-601. msb 2 bits of 8-bit digital image luminance signal input pins (for ycbcr). level conforms to itu-601. yd7 is msb. 21 nc not connected 22 to 27 i yd5 to yd0 lsb 6 bits of 8-bit digital image data input pins (for itu656 and ycbcr 27 mhz). level conforms to itu-601. lsb 6 bits of 8-bit digital image luminance signal input pins (for ycbcr). level conforms to itu-601. yd0 is lsb. 28 dgnd digital gnd 29 dv dd 3.3 v digital power supply 30 i clkx2 clock input pin (27 mhz) 31 to 38 i/o cd7 to cd0 8bit digital image chrominance signal data input pins (13.5 mhz mode). level conforms to itu-601. fixed to "0" for itu rec. 656, 27 mhz-ycbcr mode. 39 i clksel operation mode select pin. "0" : 27 mhz mode / "1" : 13.5 mhz mode.
MSM7653 ? semiconductor 6 pin descriptions (2/2) 47 i fs dac full scale adjustment pin. 48 i comp dac phase complement pin. 49 agnd analog gnd 50 o ca analog color chrominance signal output pin. 51 av dd 3.3 v analog power supply 52 o cvbso analog composite signal output pin. 53 agnd analog gnd 54 o ya analog luminance signal output pin. 55 av dd 3.3 v analog power supply 56 dgnd digital gnd 43 dgnd digital gnd 44 i test1 input pin1 for testing. normally fixed to "0". (see page 32 for details) pulled down 45 i tenb input pin2 for testing. normally fixed to "0" . pulled down 46 i/o vref reference voltage for dac 42 dv dd 3.3 v digital power supply 41 i sel2 interface select pin. itu656 : "0", ycbcr 27 mhz : "1" (see page 32 for details) pulled down pin i/o symbol description 40 i sel1 enable pin. normally fixed to "0". sleep mode "1" with test1 = "0" (see page 32 for details)
? semiconductor MSM7653 7 absolute maximum ratings parameter power supply voltage input voltage analog output current power consumption storage temperature symbol dv dd av dd v i i o p w t stg condition dv dd = 3.3 v rating C0.3 to +4.5 C0.3 to +4.5 C0.3 to +5.5 50 600 C55 to +150 unit v v ma mw c recommended operating conditions parameter power supply voltage (*1) "l" level input voltage symbol dv dd av dd v ih v il condition typ. 3.3 3.3 unit v v v operating temperature 1 ta 1 dv dd = av dd = 3.3 v 25 ?c min. 3.0 3.0 2.2 0 max. 3.6 3.6 0.8 70 external reference voltage vrefex dv dd = av dd = 3.3 v, ta = 25?c 1.25 v da current setting resistance riadj (*2) 385 w da output load resistance r l (*3) 75 w "h" level input voltage operating temperature 2 ta 2 dv dd = av dd = 3.3 v da output load = 37.5 w 25 ?c 065 (*1) supply an equal voltage to both dv dd and av dd . (*2) a volume control resistor of approx. 500 w is recommendable for adjusting the output current. when a da converter analog output is terminated with a 37.5 w load, riadj = approx. 192 w . (*3) indicates the value when riadj = 385 w (typical value).
MSM7653 ? semiconductor 8 electrical characteristics dc characteristics parameter symbol v oh condition i oh = C4 ma (*1) i ol = 4 ma (*1) typ. unit "l" level output voltage v ol i ol = 6 ma (*2) v min. 0.7v dd max. 0.4 "h" level output voltage v input leak current i i v i = gnd to dv dd m a C10 +10 output leak current i o v i = gnd to dv dd (*3) m a C10 +10 power supply current (operating) i ddo 120 ma 140 power supply current (standby) i dds reset_l = "l" 60 ma 65 i 2 c-bus sda output voltage sdav l low level, i ol = 3 ma v 0 0.4 i 2 c-bus sda output current sdai o during acknowledge ma 3 (ta = 0 to 70c, dv dd = 3.3 v 0.3 v, av dd = 3.3 v 0.3 v) internal reference voltage vrefin 1.25 v da output load resistance r l 75 w integral linearity sinl 2 lsb differential linearity sdnl 1 lsb clkx2 = 0 mhz power supply current (sleep mode) i ddsm sel2 = "h" 0.05 ma 0.03 0.5 (*1) vsync_l, hsync_l, cd[7:0] (*2) clkx1o (*3) sda ac characteristics parameter symbol condition min. typ. max. unit (ta = 0 to 70c, dv dd = 3.3 v 0.3 v, av dd = 3.3 v 0.3 v) clkx2 cycle time t s 36.4 ns input data setup time input data hold time output delay time clkx1o delay time t s1 t h1 t d1 t d2 7ns 5ns 525ns 525ns i 2 c-bus clock cycle time t c_scl ns rpull_up = 4.7 k w i 2 c-bus high level cycle t h_scl ns i 2 c-bus low level cycle t l_scl ns rpull_up = 4.7 k w 100 200 100 rpull_up = 4.7 k w
? semiconductor MSM7653 9 input/output timing clkx2 hsync_l, vsync_l, blank_l, yd, cd, ms, mode, olr, olg, olb, olc hsync_l, vsync_l clkx1o ts th1 td1 td2 ts1 invalid data valid data input timing output timing 12 789 ack 12 3-8 9 ack s start condition p stop condition change of data allowed scl sda msb t c_scl t l_scl data line stable: data valid t h_scl i 2 c-bus interface input/output timing the following figure shows i 2 c-bus basic input/output timing. i 2 c-bus basic input/output timing
MSM7653 ? semiconductor 10 block functional description 1. prologue block this block separates input data at the itu rec.656 format into a luminance signal (y) and a chrominance signal (cb & cr), and also generates information/concerning sync signals hsync_l, vsync_l, and blank_l. this block separates input data at the 27 mhz ycbcr (8-bit input) format into a luminance signal (y) and a chrominance signal (cb & cr). this block separates input data at the 13.5 mhz ycbcr (16-bit input) format into a chrominance signal cb and a chrominance signal cr. of the processed input data, luminance and chrominance signals other than valid pixel data are replaced by 8'h10 and 8'h80 respectively. 2. y limiter block this block limits the luminance input signal by clipping the lower limit of an input signal outside the itu601 standard ? signals are limited to yd = 16 when yd < 16. ? signals are limited to td = 254 when yd (input during a valid pixel period) = 255. in other cases, signals are fed as is to next processing. 3. c limiter block this block limits the chrominance signal by clipping the upper and lower limits of the input signal outside the itu601 standard. cd = 1 when cd = 0 is input during a valid pixel period. cd = 254 when cd = 255 is input during a valid pixel period. ? y level converter converts itu-601 standard luminance signal level to dac digital input level. ? u level converter converts itu-601 standard chrominance signal level to dac digital input level. ? v level converter converts itu-601 standard chrominance signal level to dac digital input level. ? yuv color generator this block generates luminance and chrominance signals from over lay color signals olr, olg and olb. control signals (cr [2:0] ) control the output content (overlay or color bar) and output level (100%, 75%, 50%, 25%). ? overlay control this block selects input image data or yuv color generator output signals. it is determined by the level of the control signal (olc, cr [2]), as shown below: (x : don't care) cr [2] = 1, olc = x: selects color bar signal (yuv color generator output signal). cr [2] = 0, olc = 1: selects overlay signal (yuv color generator output signal). cr [2] = 0, olc = 0: selects input image data.
? semiconductor MSM7653 11 ? black & blank pedestal this block adds sync signals at the luminance side to luminance signals. ? interpolator + lpf this block executes data interpolation and the elimination of high frequency components by lpf for input chrominance signals. ?i 2 c control logic this is the serial interface block based on i 2 c standard of phillips corporation. internal registers mr and cr can be set from the master side. when writing to the internal registers other than mr [1] (black level control) and cr [1:0] (overlay level), written contents are immediately set to them. it is during the vertical blanking period that written contents are set to mr [1] and cr [1:0]. ? sync generator & timing controller this block generates sync signals and control signals. this block operates in slave mode, which performs external synchronization, and in master mode, which internally generates sync signals. ? color burst generator outputs u and v components of amplitude of burst signals. ? subcarrier generator executes color subcarrier generation. ? interpolation filter (ipf) this block performs upsampling at clkx2 (double speed clkx1) for luminance signals and chrominance signals modulated with clkx1. interpolation processing is executed in this process. ? closed caption block this block generates the signal for closed caption. ? anticopy function block this block generates a macrovision auticopy signal.
MSM7653 ? semiconductor 12 input data format the signal level specified by the itu601 is input. when other signal levels than specified by the itu601 are input, the luminance signal level is clipped to 16 to 254 and the chrominance signal level to 1 to 254. for chrominance signal input, the offset binary and 2's complement formats are available by setting of internal registers. 235 16 y data digital level 100% white level black level 240(112) 16(C112) c data digital level 128(0) input luminance signal level input chrominance signal level basic pixel sampling ratio 4:2:2 is supported. 4:2:2 sampling at 8bit y/8bit cbcr input yd y1 y2 y3 y4 y5 y6 clkx1 cd cb1 cr1 cb3 cr3 cb5 cr5
? semiconductor MSM7653 13 input timing (itur656 input) the input data is fed in the encoder at the rising edge of a clock pulse. clkx2 don't care don't care sav(1st) sav(2nd) sav(3rd) sav(4th) cb0 y00 cr0 y01 cb1 y10 cr1 y11 eav(1st) eav(2nd) eav(3rd) eav(4th) data clkx1o valid data olr, olg, olb, olc input timing relationship between blank signal and input image data the blank signal is generated by the itu rec.656 standard input data. the input image data is valid when the blank signal is "h".
MSM7653 ? semiconductor 14 valid data range according to the itu rec.656 standard, the pixel data immediately from sav (4th word) to a fixed value before eva is valid. the following figure shows the relationship between the input data at the ccir rec.656 format and the sync, luminance, chrominance signals which are processed inside the encoder. y00 8'h10 luminance signal separated from input data y01 y10 y11 8'h10 eav itu rec.656 standard input data note) the values in parenthesis indicate values in pal mode. cb0, y00, cr0, y01, cb1, y10, cr1, y11.... blank_l internally generated to assure the horizontal and vertical periods cb0 8'h80 chrominance signal separated from input data composite signal cr0 cb1 cr1 8'h80 711tclkx1 (702tclkx1) 20tclkx1 (20tclkx1) 127tclkx1 (142tclkx1) 1h sync signal blank_l generated by input data 711tclkx1 (702tclkx1) 20tclkx1 (20tclkx1) 127tclkx1 (142tclkx1) 9tclkx1 (16tclkx1) sync signal hsync_l generated by input data 63tclkx1 (63tclkx1) 67tclkx1 (67tclkx1) 4tclkx1 (4tclkx1) sync signal vsync_l (1/2) generated by input signal 1/2h sync signal vsync_l (0h) generated by input signal 11tclkx1 (4tclkx1) 4tclkx2 1716tclkx2 (ntsc)/1728clkx2 (pal) 1440t (ntsc/pal) 136tclkx1 (146tclkx1) sav 4tclkx2 eav relationship between input data and sync signal, luminance signal, chrominance signals
? semiconductor MSM7653 15 clock timing2 (8bit y/8bit cbcr input) input data timing input data and sync signals are fed into the encoder at the rising edge of clkx2. input data is handled as valid pixel data when t start passes after the falling edge of hsync_l. chrominance signal of input data at this time is regarded as cb. don't care don't care yd, cd, olr, olb, olg, olc hsync_l clkx2 blank_l t start t act t s1 t h1 valid data active video line video data input timing input data is recognized as valid pixel data when input signal blank_l is "h" in the t act period. when blank_l is "h" during the blanking period, however, input data is not output as valid pixel data since processing to maintain blanking period is internally in-progress. the values of t start differ slightly between in master mode and in slave mode. the values of t start are as follows. in ycbcr format input mode, the values of t start are the same, in 8 bit (y) + 8 bit (cbcr) mode or in 8 bit (ycbcr) mode. operation mode itu 601 ntsc itu 601 pal in master mode t sta (ts) 250 280 operation mode itu 601 ntsc itu 601 pal in slave mode t sta (ts) 260 290 t sta C t s1 = t start
MSM7653 ? semiconductor 16 timing of input data to hsync_l input timing when blank_l is input input timing at 27 mhz in ycbcr format timing of input data to hsync_l input timing when blank_l is input input timing at 13.5 mhz in ycbcr format clkx2 clkx1o hsync_l olr,olg, olb, olc yd invalid data invalid data invalid data valid data invalid data cb0 y00 cr0 y01 cb1 y10 t start t act clkx2 blank_l yd cb0 y00 cr0 y01 cb1 clkx2 clkx1o hsync_l olr,olg, olb, olc cd invalid data invalid data invalid data valid data invalid data cb0 cr0 cb1 yd invalid data invalid data y0 y1 y2 t start t act clkx2 blank_l yd y0 y1 y2 cd cb0 cr0 cb1
? semiconductor MSM7653 17 internal synchronization output timing input and output timing of hsync_l and vsync_l in master mode is as follows. t d1 t d1 clkx2 hsync_l vsync_l output timing of internal synchronization, hsync_l and vsync_l ya vsync_l 5235245251234567 17 18 output timing of internal synchronization vsync_l
MSM7653 ? semiconductor 18 output format the timing conforms to the itu624 standard. in the ntsc operation mode, the existence/non-existence of setup level is selected by setting of internal regsiters. data level on the dac input terminal: when the contents of 100% luminance order color bar are input into the encoder, the input level is as follows. C20 0 7.5 11 20 30 41 59 70 89 100 133 C40 114 224 266 285 338 390 450 549 610 715 775 957 4 dac data lumi (ire) composite wave form (ntsc) white yellow cyan green magenta red blue black ntsc composite signal (setup 7.5)
? semiconductor MSM7653 19 0 11 30 41 59 70 89 100 C40 224 285 390 450 549 610 715 775 4 dac data lumi (ire) white yellow cyan green magenta red blue black y wave form (ntsc) ntsc y signal output (setup 0) C20 0 C59 C63 20 44 59 63 C44 402 512 188 166 622 754 836 858 270 dac data lumi (ire) yellow cyan green magenta red blue color burst c wave form (ntsc) ntsc c signal output
MSM7653 ? semiconductor 20 C21.5 0 11 21.5 30 41 59 70 89 100 133 C43 123 241 302 359 406 467 566 627 731 792 973 4 dac data lumi (ire) white yellow cyan green magenta red blue black composite wave form (pal) pal composite signal 0 11 30 41 59 70 89 100 C43 241 302 406 467 566 627 731 792 4 dac data lumi (ire) white yellow cyan green magenta red blue black y wave form (pal) pal y signal output
? semiconductor MSM7653 21 C21.5 0 C59 C63 21.5 44 59 63 C44 394 512 188 166 630 754 836 858 270 dac data lumi (ire) yellow cyan green magenta red blue color burst c wave form (pal) pal c signal output
MSM7653 ? semiconductor 22 ntsc (interlaced) 25926026126226312345678 171819 field 1 reference sub-carrier phase negative half cycle burst relative C180 to b-y axis positive half cycle burst relative 180 to b-y axis a b c d e 25926026126226312345678 171819 field 2 reference sub-carrier phase a b c d e 25926026126226312345678 171819 field 3 reference sub-carrier phase a b c d e 25926026126226312345678 171819 field 4 reference sub-carrier phase a b c d e output timing (interlaced ntsc)
? semiconductor MSM7653 23 output timing (interlaced ntsc) period odd field (even field) 259.5 to 262.5h 1 to 3h 4 to 6h 1 to 6,259.5 to 262.5h 1 to 17,259.5 to 262.5h name first equalizing pulse period (3h) vertical synchronization period (3h) second equalizing pulse period (3h) burst pause period vertical blanking period (20h) symbol a b c d e
MSM7653 ? semiconductor 24 ntsc (non-interlaced) output timing (non-interlaced ntsc) period continuous odd ? even field 261 to 262h 1 to 3h 4 to 6h 261 to 6h 261 to 17h name first equalizing pulse period (2h) vertical synchronization period (3h) second equalizing pulse period (2h) burst pause period vertical blanking period (19h) symbol a b c d e output timing (non-interlaced ntsc) 26026126212345678 171819 continuous odd field reference sub-carrier phase negative half cycle burst relative C180 to b-y axis positive half cycle burst relative 180 to b-y axis a b c d e 26026126212345678 171819 reference sub-carrier phase a b c d e 26026126212345678 171819 reference sub-carrier phase a b c d e continuous even field 26026126212345678 171819 reference sub-carrier phase a b c d e
? semiconductor MSM7653 25 output timing (interlaced pal) output timing (interlaced pal) period field 1,5 311 to 312.5h 1 to 2.5h 2.5 to 5h 1 to 6,310 to 312.5h 1 to 22.5,311 to 312.5h name first equalizing pulse period (2.5h) vertical synchronization period (2.5h) second equalizing pulse period (2.5h) burst pause period vertical blanking period (25h) symbol a b c d e field 3,7 311 to 312.5h 1 to 2.5h 2.5 to 5h 1 to 5,311 to 312.5h 1 to 22.5,311 to 312.5h field 2,6 311 to 312.5h 1 to 2.5h 2.5 to 5h 1 to 5.5,308.5 to 312.5h 1 to 22.5,311 to 312.5h field 4,8 311 to 312.5h 1 to 2.5h 2.5 to 5h 1 to 6.5,309.5 to 312.5h 1 to 22.5,311 to 312.5h 30931031131231312 345678 232425 field 1,5 burst phase +135 +v burst phase -135 -v a b c d e field 2,6 30931031131231312 345678 232425 a b c d e 30931031131231312 345678 232425 field 3,7 a b c d e field 4,8 30931031131231312 345678 232425 a b c d e pal (interlaced)
MSM7653 ? semiconductor 26 pal (non-interlaced) 31031131212345678 232425 continuous odd field burst phase +135 +v burst phase -135 -v a b c d e 309 31031131212345678 232425 a b c d e 309 31031131212345678 232425 continuous even field a b c d e 309 31031131212345678 232425 a b c d e 309 output timing (non-interlaced pal) output timing (non-interlaced pal) period continuous odd ? even field 311 to 312h 1 to 2.5h 2.5 to 5h 311 to 6h 311 to 22h name first equalizing pulse period (2h) vertical synchronization period (2.5h) second equalizing pulse period (2.5h) burst pause period vertical blanking period (24h) symbol a b c d e
? semiconductor MSM7653 27 horizontal blanking period setting content of equalizing pulse vertical synchronization period (ts is sampling clock cycle in each mode) itu 601 ntsc itu 601 pal q 31ts 32ts w 365ts 369ts e 64ts 63ts 1/2h 429ts 432ts q w e 1/2h 1/2h q equalizing pulse width w vertical sync pulse width e serration q blanking level w (synchronizing + blanking level) (2/3) e (synchronizing + blanking level) (1/3) r synchronzing level r e w q equal q w e r t 1h q horizontal sync pulse width w burst signal output period e burst signal start r horizontal blanking period (excluding front porch) t front porch start q synchronzing level w (synchronizing + blanking level) (1/3) e (synchronizing + blanking level) (2/3) r blanking level t peak to peak value of burst r e w q t setting content of horizontal blanking period (ts is sampling clock cycle in each mode) itu601 ntsc itu601 pal q 63ts 63ts w 31ts 31ts e 71ts 75ts r 127ts 142ts t 838ts 844ts total dots/1h 858 864 setting content of horizontal blanking period
MSM7653 ? semiconductor 28 setup level setting when the ntsc operation mode is selected, one of the two kinds of setup level can be selected by setting of registers. when the setup level 0 is selected, the black-to-white is 100ire. when the setup level 7.5ire is selected, the black-to-white is 92.5ire. however, this setup function is valid only for the ntsc mode and invalid for the pal mode. color bar generation function the 75% luminance order color bar or 100% luminance order color bar is output by setting internal registers. the output timings for each color bar color is as follows. contents of color bar output timing setting itu601 ntsc itu601 pal 1h 858ts 864ts u 750ts 757ts y 661ts 670ts t 572ts 582ts r 483ts 494ts e 394ts 406ts w 305ts 318ts q 216ts 230ts hblank 127ts 142ts operation mode (ts : sampling block period) white q w e r t y u yellow cyan green magenta red blue black output timing of each color bar color
? semiconductor MSM7653 29 i 2 c bus format basic input format of i 2 c-bus interface is shown below. as described above, it is possible to read and write data from subaddress to subaddress continuously. reading from and writing to discontinuous addresses is performed by repeating the acknowledge and stop condition formats after data 0. if one of the following matters occurs, the encoder will not return "a" (acknowledge). ? the slave address does not match. ? a non-existent subaddress is specified. ? the read/write attribute of a register does not match "x" (read : 1/write : 0 control bit). the input timing is shown below. slave address s subaddress a data 0 a a ..... data n a p s slave address a subaddress data n description start condition slave address 1000100x (adrs pin : 0) or 1000110x (adrs pin : 1), acknowledge. generated by slave subaddress byte data byte and acknowledge continues until data byte stop condition is met. symbol p stop condition the 8th bit is r (1)/w (0) signal. 12 789 ack 12 3-8 9 ack s start condition p stop condition change of data allowed scl sda msb t c_scl t l_scl data line stable: data valid t h_scl i 2 c-bus basic input/output timing
MSM7653 ? semiconductor 30 closed caption function the closed caption function based on the nci standard is available. the caption information on each line is multiplexed as a 26-cycle signal which is synchronized at 503 khz. each cycle is described below. cycles 1 to 7 clock-run-in period 7-cycle clock signal to synchronize caption data with caption information. cycles 8 to 10 start code fixed signal with logical level "001" cycles 11 to 26 caption information 2-byte multiplex information with combination of the ascii code bits 0 - 6 and the 7odd parity bit. the first byte is multiplexed in cycles 11 to 18 and the second byte is multiplexed in cycles 19 to 26, starting from lsb. the output timing when data is multiplexed by the closed caption function is shown below. 1 clock run in 13.9 m s (reference) cycle 50ire 234567891011121314151617181920212223242526 50ire 20ire C40ire 0ire 10.0 m s (reference) start code 6.0 m s (reference) 16-bit information transition time 31.8 m s (reference) 61.7 m s (reference) caption signal transition time transition time : ns 50% 100%
? semiconductor MSM7653 31 internal registers the register (id number) for the anticopy function and the register (ccstat) for the closed caption can be read. the registers other than id number can be written. details of the internal registers are described below. (values marked * are set by default.) register name r/w sub- address default value item to be set description mr (mode register) write only 00 00 mr[4] override switching between the external terminal and internal register settings (for the operation mode) *0 : external terminal setting enabled 1 : internal register setting enabled mr[3] chroma format chrominance signal input format *0 : offset binary 1 : 2's complement mr[2] black level control black level setup note : valid in ntsc mode only *0 : black level 0ire 1 : black level 7.5ire mr[0] video mode select operation mode switching *0 : itu601 ntsc 1 : itu601 pal cr (command register) write only 01 03 cr[4] undefined cr[3] interlace scanning method *0 : interlace 1 : non-interlace cr[1:0] overlay level overlay signal/adjusting luminance order color bar output level control 00 : 25% 01 : 50% 10 : 75% *11 : 100% mr[1] master/slave master or slave operation select *0 : slave 1 : master cr[2] color bar adjusting luminance order color bar output control *0 : input image data or overlay data 1 : luminance order color bar
MSM7653 ? semiconductor 32 ccodt0 write only 04 00 ccodt0[7:0] 1st byte of c.c. data, odd field first byte closed caption data in odd-number field ccodt1 write only 05 00 ccodt1[7:0] 2nd byte of c.c. data, odd field second byte closed caption data in odd-number field ccedt0 write only 06 00 ccedt0[7:0] 1st byte of c.c. data, even field first byte closed caption data in even-number field ccedt1 write only 07 00 ccedt1[7:0] 2nd byte of c.c. data, even field second byte closed caption data in even-number field ccstat read/ write 08 00 ccstat[0] odd field c.c. status odd-number field status *0 : ccodt0, ccodt1 writing completed 1 : odd field c.c. bytes encode completed ccstat[1] odd field c.c. status even-number field status *0 : ccedt0, ccedt1 writing completed 1 : even field c.c. bytes encode completed register name r/w sub- address default value item to be set description ccen write only 02 00 ccen[0] closed caption enable closed caption function on/off control *0 : c.c. encoding off 1 : odd field encoding on 2 : even field encoding on 3 : both field encoding on ccln write only 03 11 ccln[4:0] closed caption line number closed caption data insertion line number setting ntsc : ccln + 4 pal : ccln + 1 operation mode setting by pin control the contents of control using test1, sel1, sel2, clksel, and ms are shown below. test1 0 : normal operation 1 : test mode sel1 0 : normal operation 1 : sleep mode sel2 0 : itu rec. 656 1 : y cb cr clksel 0 : 27 mhz 1 : 13.5 mhz ms 0 : slave 1 : master test1 sel1 sel2 clksel ms operation mode 0 0 0 0 0 itur656 slave 0 0 0 1 0 13.5 mhz ycbcr slave 0 0 0 1 1 13.5 mhz ycbcr master 0 0 1 0 0 27 mhz ycbcr slave 0 0 1 0 1 27 mhz ycbcr master 0 1 x x x sleep mode x : don't care
? semiconductor MSM7653 33 filter characteristics the characteristics of lpf used for color signal processing and interpolation filters used for upsampling processing are shown below. lpf for 422 color signals the following shows the characteristics when the clock frequency is 13.5 mhz. C100 C80 C60 C40 C20 0 01234567 422 interpolation + lpf frequency characteristic frequency [mhz] level [db] C100 C80 C60 C40 C20 0 02468101214 up sampling filter frequency characteristic frequency [mhz] level [db] interpolation the following shows the characteristics when the clock frequency is 27 mhz. (note) the characteristics of these filters are based on design data.
MSM7653 ? semiconductor 34 application circuit example recommended analog output circuit 150 w 3.6 m h 164 pf output ya ca cvbso 150 w 164 pf 0.1 m f 0.1 m f 75 w 560 w 560 w Cavcc +avcc 1000 m f + + C lpf (toko-make 621ljn-1471 is recommended.) clksel sel1 dip sw olr olg olb olc overlay controller blank_l hsync_l vsync_l clkx1o cd[7:0] cd[7:0] yd[7:0] yd[7:0] MSM7653 clkx2 v ref fs comp ya lpf amp r1 cvbso lpf amp r1 ca lpf amp r1 c c = 0.1 m f typ. 1.25 v r c scl sda i 2 c controller r l r l 5 v or 3.3 v dv dd 3.3 v av dd 3.3 v 5 v or 3.3 v 3.3 v dgnd agnd outsel mode ms sel2 r c = 500 w vr note: the termination of a da converter analog output with a 37.5 w load eliminates need for an amp.
? semiconductor MSM7653 35 package dimensions (unit : mm) 56-pin plastic qfp
MSM7653 ? semiconductor 36 notice 1. the information contained herein can change without notice owing to product and/or technical improvements. before using the product, please make sure that the information being referred to is up-to-date. 2. the outline of action and examples for application circuits described herein have been chosen as an explanation for the standard action and performance of the product. when planning to use the product, please ensure that the external conditions are reflected in the actual circuit, assembly, and program designs. 3. when designing your product, please use our product below the specified maximum ratings and within the specified operating ranges including, but not limited to, operating voltage, power dissipation, and operating temperature. 4. oki assumes no responsibility or liability whatsoever for any failure or unusual or unexpected operation resulting from misuse, neglect, improper installation, repair, alteration or accident, improper handling, or unusual physical or electrical stress including, but not limited to, exposure to parameters beyond the specified maximum ratings or operation outside the specified operating range. 5. neither indemnity against nor license of a third party's industrial and intellectual property right, etc. is granted by us in connection with the use of the product and/or the information and drawings contained herein. no responsibility is assumed by us for any infringement of a third party's right which may result from the use thereof. 6. the products listed in this document are intended for use in general electronics equipment for commercial applications (e.g., office automation, communication equipment, measurement equipment, consumer electronics, etc.). these products are not authorized for use in any system or application that requires special or enhanced quality and reliability characteristics nor in any system or application where the failure of such system or application may result in the loss or damage of property, or death or injury to humans. such applications include, but are not limited to, traffic and automotive equipment, safety devices, aerospace equipment, nuclear power control, and medical equipment including life-support systems. 7. certain products in this document may need government approval before they can be exported to particular countries. the purchaser assumes the responsibility of determining the legality of export of these products and will take appropriate and necessary steps at their own expense for these. 8. no part of the contents cotained herein may be reprinted or reproduced without our prior permission. copyright 1998 oki electric industry co., ltd.

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